The present invention relates to a semiconductor memory circuit, and particularly to a static type semiconductor memory circuit controlled by a chip select signal.
Static type memory circuits have been utilized in various fields as high speed memories.
A static memory is controlled by a chip select signal (CS) between an active state for achieving a reading or writing operation and an inactive state in which the memory is set at a stand-by mode in order to implement a high speed operation with a low power consumption. The chip select signal CS is received by a clock input buffer of the memory and the clock input buffer generates an internal control signal for actually controlling peripheral circuits such as addressing circuits and an output circuit included in the memory.
When the chip selection signal is brought into its active level, e.g. low level, the internal control signal is set at an active level, e.g. low level so that the peripheral circuits are enabled for a reading or writing operation. While, when the chip selection signal is changed into its inactive state, the internal control signal is also set at its inactive level (e.g. high level) so that the peripheral circuits are disenabled and set at a stand-by mode.
In order to achieve a high-speed operation, it is necessary to generate the active level of the internal control signal quickly as soon as the chip select signal is changed to the active level from the inactive level. Therefore, the clock input buffer receiving the chip select signal has been designed to generate the active level of the internal control signal rapidly in response to the change of the chip select signal from the inactive level to the active level, as compared to the case where the clock input buffer generates the inactive level of the internal control signal in response to the change of the chip select signal from the active level to the inactive level.
Namely, in the case where the active level and the inactive level of the internal control signal are a low level and a high level, respectively, a lower potential side drive transistor for pulling down the output of the clock input buffer is designed to have a large current ability while a higher potential side drive transistor for pulling-up the output of the clock input buffer is designed to have a small current ability.
Accordingly, the clock input buffer generates the active level of the internal control signal rapidly to enable the peripheral circuit. However, the clock input buffer generates the inactive level of the input control signal with a relatively large delay time from a time when the chip select signal has changed from the active level to the inactive level, and therefore the peripheral circuits are still enabled for the period corresponding to the above delay time even after the chip select signal has changed to the inactive level. Thus, the memory inevitably produces an output signal after the chip select signal has changed to the inactive level.
In general, an output terminal of a memory circuit is connected to a bus line to which another functional circuit is connected, and therefore, the above phenomenon that the memory produces a read out signal after the chip select signal thereto has changed to the inactive level makes the effective speed of the memory slow and the utilization ratio of the bus line is also lowered.